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CXB1562AQ
2R IC for Optical Fiber Communication Receiver
Description The CXB1562AQ achieves the 2R optical-fiber communication receiver functions (Reshaping and Regenerating) on a single chip. This IC is also equipped with the signal interruption alarm output function, which is used to discriminate the existence of data input. 32 pin QFP (Plastic)
Features * Auto-offset canceler circuit * Signal interruption alarm output * 2-level switching function of identification maximum voltage amplitude for alarm block * Single 5V power supply Applications * FDDI * SONET/SDH * ESCON * Fiber channel
: 125Mb/s : 155.52Mb/s : 200Mb/s : 265.625Mb/s
Absolute Maximum Ratings * Supply voltage * Storage temperature * Input voltage difference : I VD - VD I * SW input voltage * Output current (Continuous) (Surge current)
VCC - VEE Tstg Vdif Vi IO
-0.3 to +7.0 -65 to +150 0.0 to +2.5 VEE to VCC 0 to 50 0 to 100
V C V V mA mA
Recommended Operating Conditions * Supply voltage VCC - VEE * Termination voltage (for data/alarm) VCC - VT1 * Termination voltage (for alarm 2) VT2 * Termination resistance (for data/alarm) RT1 * Termination resistance (for alarm 2) RT2 * Operating temperature Ta Structure Bipolar silicon monolithic IC
5.00.5 1.8 to 2.2 VEE 45 to 55 460 to 560 -40 to +85
V V V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E94930B6Z
CXB1562AQ
Block Diagram and Pin Configuration
VccDA
VccD
VccDA
24 N.C. 25
23
22
21
20
19
18
17
N.C.
SD
SD
Q
Q
16 N.C. 26 15 N.C. 27 Alarm Block 14 Limiting Amplifier Block
TM
VccD
VEED
CAP3 28
13
VccA
peak hold
CAP2 29
peak hold
12
VEEA
V
DOWN 30
R2
R2
11 CAP1 UP 31 VccA 32 DR RP 1 RR 2 3 4 5 6 7 8 R1 R3 R1 R4 10 9 R2K R1K
-2-
CAP1
VEEI
SW
VccP
VccR
D
VCCA
D
CXB1562AQ
Pin Description Typical pin Pin No. Symbol voltage (V) DC AC 1 VCCP
Equivalent circuit
Description
50k
Positive power supply for external power supply. 2 VCCR
32 10 1 2 VccA 993 110.3 110.3 31
3
VEEI
-5V
30 Vcs SW VEEA 3
Generates the default voltage between UP and DOWN. The voltage (8.0mV for input conversion) can be generated between UP and DOWN (Pins 30 and 31) as alarm setting level by connecting this pin to VEEA.
VCCA
150k
0V 4 SW
(OPEN)
100k 4 VREF
or -5V
Switches the identification maximum voltage amplitude. High voltage when open; the identification maximum voltage amplitude becomes 50mVp-p. Low voltage when connecting this pin to VEE; the amplitude becomes 20mVp-p.
VEEA
5
D
-1.3V
-0.9V to -1.7V -0.9V to -1.7V
200 5 6 200 10k 100p 200 10k 200 2k 10 1k 9 8 11 VCCA
6
D
-1.3V
Limiting amplifier block input. Be sure to make this input with AC coupled.
7 8
VCCA
0V
Positive power supply for analog block. Pins 8 and 11 connect a capacitor which determines the cut-off frequency for feedback block, and 1k is connected between Pins 8 and 9; 2k between Pins 10 and 11. A resistor which is to be inserted in parallel with a capacitor can be selected 5 ways by external wiring, and DC feedback can be varied.
CAP1 -1.8V R1K
1.5k
9
1.5k VEEA
10
R2K
11
CAP1 -1.8V -3-
CXB1562AQ
Typical pin Pin No. Symbol voltage (V) DC AC 12 13 14 15 16 17 VEEA VCCA VEED VCCD TM N.C -0.9V to -1.7V -5V 0V -5V 0V -3.0V
14
Equivalent circuit
Description Negative power supply for analog block. Positive power supply for analog block. Negative power supply for digital block. Positive power supply for digital block.
16
Chip temperature monitor. No connected.
VCCDA
18
Q
19
Data signal output. Terminate this pin in 50 at VTT = -2V.
19
Q
-0.9V to -1.7V
18 VEED
20
VCCDA
0V
VCCDA
Positive power supply for output buffer. -0.9V to -1.7V
21
SD
21
Alarm signal output. Terminate this pin in 50 at VTT = -2V.
22
SD
-0.9V to -1.7V
22 VEED
23 24 25 26 27
VccDA VccD N.C N.C N.C
0V 0V
Positive power supply for digital block. Positive power supply for digital block.
No connected.
-4-
CXB1562AQ
Typical pin Pin No. Symbol voltage (V) DC AC
Equivalent circuit
Description
29
28 VCCA
28
CAP3 -1.8V
80
80
29
CAP2 -1.8V
5A
5A VEEA
Connects a peak hold circuit capacitor for alarm block. 470pF should be connected to VccA each. CAP2 pin Peak hold capacitor connection for alarm level setting block. CAP3 pin Peak hold capacitor connection for limiting amplifier signal.
10p
10p
VccA
30
-0.84V (for DOWN VEEI = -5V)
993 110.3 110.3 31 30
31
UP
-0.8V (for VEEI = -5V)
Vcs
SW VEEA
Connects a resistor for alarm level setting. Default voltage can be generated without an external resistor by shorting the VEEI pin to VEEA.
3
32
VccA
0V
Positive power supply for analog block.
-5-
CXB1562AQ
Electrical Characteristics * DC characteristics (VCC = GND, VEE = -5V10%, Ta = -40 to +85C, VCC = VCCD, VCCDA, VCCA VEE = VEED, VEEA) Item Power supply Q/Q SD/SD High output voltage Q/Q SD/SD Low output voltage SD/SD High output voltage 2 SD/SD Low output voltage 2 SW High input voltage SW Low input voltage SW High input current SW Low input current D/D input resistance Internal resistance 1 for alarm level setting Internal resistance 2 for alarm level setting Resistance between VccA and VccP Resistance between VccA and VccR Pare ratio of internal resistance 2 for alarm level setting Resistance between CAP1 and R1K Resistance between CAP1 and R2K Symbol IEE VOH VOL VOHb VOLb VIH VIL IIH IIL Rin Ra1 Refer to Fig. 3. -60 1125 745 82.7 1500 993 110.3 10 37.5 Ra2A/Ra2B 0.97 745 1489 993 1986 50 62.5 1.03 1241 2482 k 1875 1241 137.9 Conditions RT1 = 50, VT1 = -2V termination RT1 = 50, VT1 = -2V termination Ta = 0 to 85C RT2 = 510, VEE termination Ta = 0 to 85C Min. -50 -1025 -1810 -1075 -1860 -1900 VEE Typ. -37 Max. -28 -880 -1620 -830 -1570 0 -2500 2 A mV Unit mA
Ra2A, B Refer to Fig. 3. RP RR Ra2 R3 R4
-6-
CXB1562AQ
* AC characteristics (VCC = GND, VEE = -5V10%, Ta = -40 to +85C, VCC = VCCD, VCCDA, VCCA VEE = VEED, VEEA) Item Maximum input voltage amplitude Amplifier gain (except for output buffer) Identification maximum voltage amplitude of alarm level Hysteresis width SD response assert time SD response deassert time SD response assert time for alarm level default SD response deassert time for alarm level default Alarm setting level for default Propagation delay time Q/Q SD/SD rise time Q/Q SD/SD fall time 1 2 3 4 Symbol Vmax GL VminA1 VminA2 P Tas Tdas Tasd Tdasd Vdef TPD Tr Tf Low High1 High Low2 Low High3 High Low4 UP/DOWN pins; Open, connect VEEI to VEE. D to Q RT1 = 50, VT1 = -2 V termination VEE = -5V, 20% to 80% Conditions Single-ended input IC internal amplitude of 400mV SW pad: Low, single-ended input SW pad: Open High, single-ended input Min. 1600 60 20 mVpp 50 4 0 2.3 0 2.3 6.6 0.95 0.45 0.45 8.0 1.65 6 7 100 100 100 100 9.3 2.75 1.6 1.6 ns mV s dB Typ. Max. Unit mVpp dB
VUP - VDOWN = 100mV, Vin = 100mVpp (single ended), SW pin: High Peak hold capacitance (CAP2, CAP3 pins) of 470pF; connect VEEI to VEE. VUP - VDOWN = 100mV, Vin = 1Vpp (single ended), SW pin: High Peak hold capacitance (CAP2, CAP3 pins) of 470pF; connect VEEI to VEE. Vin = 50mVpp (single ended), SW pin: Low Peak hold capacitance (CAP2, CAP3 pins) of 470pF; connect VEEI to VEE. Vin = 1Vpp (single ended), SW pin: Low Peak hold capacitance (CAP2, CAP3 pins) of 470pF; connect VEEI to VEE.
-7-
CXB1562AQ
DC Electrical Characteristics Measurement Circuit
VT1
-2V
V
51 51
V
V
51 51
V
24 25
23
22
21
20
19
18
17
16 26 15 27 Alarm Block 28 Limiting Amplifier Block
C3
14
29
peak hold
peak hold
C3
13
12
R2
V
30
R2
11
V
31 32 DR
R1
R4 10 9
V V
C2
R1
R3
V
V
RP 1
RR 2 3 4 5 6 7 8
V
V
V A
C1 VS C1
V
VD VEE
A
-5V
-8-
CXB1562AQ
AC Electrical Characteristics Measurement Circuit
Oscilloscope 50 input
Z0 = 50 Z0 = 50
Z0 = 50
Z0 = 50
24 25
23
22
21
20
19
18
17
16 26 15 27 Alarm Block 28 Limiting Amplifier Block
470pF
14
peak hold
470pF 29
13
peak hold
12
R2
REX1
V
31 32
V
30
R2
11 R1 DR RP 1 RR 2 3 4 5 6 7 8 R4 10 9 R1 R3 0.22F
REX2
0.022F
0.022F VEE -3V VCC +2V
-9-
CXB1562AQ
Application Circuit
VT1
-2V
51
51
51
51
24 25
23
22
21
20
19
18
17
16 26 15 27 Alarm Block 28 470pF Limiting Amplifier Block
C3
14
peak hold
29 470pF
peak hold
C3
13
12
R2
V
30
R2
11 31 32 DR RP 1 RR 2 3 4 5 6 7 8 R1 R3 R1 R4 10 9 C2 0.22F
C1 0.022F
C1 0.022F
VEE
-5V
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 10 -
CXB1562AQ
Notes on Operation 1. Limiting amplifier block The limiting amplifier block is equipped with the auto-offset canceler circuit. When external capacitors C1 and C2 are connected as shown in Fig. 1, the DC bias is set automatically in this block. External capacitor C1 and IC internal resistor R1 determine the low input cut-off frequency f2 as shown in Fig. 2. Similarly, external capacitor C2 and IC internal resistor R2 determine the high cut-off frequency f1 for DC bias feedback. Since peaking characteristics may occur in the low frequency area of the amplifier gain characteristics depending on the f1/f2 combination, set the C1 and C2 so as to avoid the occurrence of peaking characteristics. The target values of R1 and R2 and the typical values of C1 and C2 are as indicated below. When a single-ended input is used, provide AC grounding by connecting Pin 6 to a capacitor which has the same capacitance as capacitor C1. R1 (internal): 1.5k R2 (internal): 10k f2: 4.8kHz f1: 72Hz C1 (external): 0.022F C2 (external): 0.22F 1k is incorporated between Pins 8 and 9; 2k between Pins 10 and 11. A resistance value which is to be inserted in parallel with a capacitor f2 can be selected 5 ways (, 3k, 2k, 1k, 1k//2k) by external wiring, and DC feedback can be varied.
D C1
5 To IC interior 6 C1 R1 8 R3 9 C2 10 R4 11 R2 R2 R1
Fig. 1
Feedback frequency response
Amplifier frequency response
Gain
f1
f2 Frequency
Fig. 2 - 11 -
CXB1562AQ
2. Alarm block In order to operate the alarm block, give the voltage difference between Pins 30 and 31 to set an alarm level and connect the peak hold capacitor C3 shown in Fig. 3. This IC has two setting methods of alarm level; one is to connect VEE to Pin 3 and leave Pins 30 and 31 open to set an alarm level default value (8mV for input conversion). The other is to connect Pin 3 to VEE and set a desired alarm level using the external resistors REX1 and REX2 and REX3 shown in Fig. 3. Connect REX1 between Pins 30 and 31, or between Pin 30 and VCC when less alarm level is desired to be set than its default value; connect REX2 between Pin 31 and Vcc potential when more alarm level is desired to be set than its default value. However, the Pin 31 voltage must be higher than that of Pin 30. Refer to Figs. 5, 8 to 11 for this alarm level setting. This IC also features two-level setting of identification maximum voltage amplitude. The amplitude is set to 50mVp-p when Pin 4 is left open (High level) and it is set to 20mVp-p when Pin 4 is Low level. Therefore, noise margin can be increased by setting Pin 4 to Low level when small signal is input. The relation of input voltage and peak hold output voltage is shown in Fig. 6. In the relation between the alarm setting level and hysteresis width, the hysteresis width is designed to maintain a constant gain (design target value: 6dB) as shown in Fig. 4. The C3 capacitance value should be set so as to obtain desired assert time and deassert time settings for the alarm signal. The electrical characteristics for the SD response assert and deassert times are guaranteed only when the waveforms are input as shown in the timing chart of Fig. 7. The typical values of REX1, REX2, REX3 and C3 are as follows: (Approximately 10pF capacitor is built in Pins 28 and 29 each.) REX1 : 217 (when the alarm level is set to 4mV for input conversion.) REX2 : 634 (when the alarm level is set to 19mV for input conversion.) REX3 : 4k (when the alarm level is set to 4mV for input conversion.) C3 : 470pF The table below shows the alarm logic. Optical signal input state Signal input Signal interruption SD High level Low level SD Low level High level
Ra1, Ra2A and Ra2B values are typical values. VCCA Ra1 Ra2A 110.3 993 Ra2B 110.3 Vcs
From Limiting Amplifier
Peak hold
SD SD Peak hold
VccA V 4 3 31 30 10p 29 C3 REX2 Vcc REX1 REX3 Vcc Vcc Vcc 28 C3
VccA 10p
IC interior 31 IC exterior 30 3
Fig. 3 - 12 -
CXB1562AQ
VDAS Deassert level VAS Assert level High level
25 VAS 20 SW = High SW = Low
SD output
VAS, VDAS [mV]
Low level VDAS Small 3dB 3dB Alarm setting input level Hysteresis Input electrical signal amplitude VAS Large
15 VDAS 10
5
0 0 20 40 60 80 100 Voltage between Pins 30 and 31 [mV]
Fig. 4
Fig. 5
Peak hold output voltage
SW Low
SW Open High
0
20mVpp
50mVpp
Input voltage [Vp-p]
Fig. 6
Data input (D)
Hysteresis width
Alarm setting level
Data output (Q)
Alarm output (SD)
Assert time
Deassert time
Fig. 7
- 13 -
CXB1562AQ
TM pin temperature characteristics
2800 2600 2400 40 35
REX1-VUD temperature characteristics data
2200 2000 1800 1600 1400 -50 Iin = 100A Iin = 1mA Iin = 5mA -25 0 25 50 75 100 125
Vup-Vdown [mV]
30 25 20 15 10 5 -40C 27C 85C 125C 0 400 800 1200 1600 2000
TM-VEE [mV]
Tj [C]
REX1 []
Fig. 8
Fig. 9
REX2-VUD temperature characteristics data
130 120 110 -40C 27C 85C 125C 40 35 30
REX3-VUD temperature characteristics data
Vup-Vdown [mV]
100 90 80 70 60 50 40 0 1000 2000 3000 4000 5000 6000 7000
Vup-Vdown [mV]
25 20 15 10 5 0 0 5 10 15 REX3 [k] 20 -40C 27C 85C 125C 25 30
REX2 []
Fig. 10
Fig. 11
3. Others Pay attention to handling this IC because its electrostatic discharge strength is weak.
- 14 -
CXB1562AQ
Example of Representative Characteristics
Bit Error Rate vs. Data Input Level
10-6 140 10-7 120 100 80 60 40 20 1.7 0 1 10 100 1000
Output RMS Jitter vs. Data Input Level
Output RMS Jitter [pS]
VEE = -5.0V Ta = 27C D = 155.52Mbps pattern: PRBS223-1
Bit Error Rate
10-8 10-9 10-10 10-11 10-12 1. 1 VEE = -5.0V Ta = 27C D = 155.52Mbps pattern: PRBS223-1 1. 2 1. 1.4 1. 1. 3 5 6 Data Input Level [mVpp]
Data Input Level [mVpp]
Fig. 12
Q Output Waveform
Fig. 13
-520mV VEE = -5.0V Ta = 27C D = 155.52Mbps, 2mVp-p pattern: PRBS223-1 -1320mV
X Axis : 200 mV / div Y Axis : 2 ns / div
16ns
26ns
-2120mV 36ns
Fig. 14
- 15 -
CXB1562AQ
Package Outline
Unit: mm
32PIN QFP (PLASTIC)
9.0 0.2 + 0.3 7.0 - 0.1 24 17 + 0.35 1.5 - 0.15
0.1
25
16
32
9
+ 0.2 0.1 - 0.1
1 0.8 + 0.15 0.3 - 0.1
8 + 0.1 0.127 - 0.05 0 to 10
0.12 M
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-32P-L01 QFP032-P-0707-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
EPOXY RESIN SOLDER PLATING 42 ALLOY 0.2g
- 16 -
0.50
(8.0)

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